The present invention relates to cache memories, and particularly to the use of cache memories to store data in an image processing system.
Data processing apparatus commonly store data and program instructions in a memory device. The memory may be any of several forms, such as solid state circuits, floppy diskettes or hard disks. The amount of time required to retrieve information from a memory varies depending upon the type of memory device and how many other components are competing for access to the memory. The physical relationship of the storage location of newly sought data to that for the last item of data acquired from the memory also can affect the retrieval time.
At times, the speed at which a program executes is in large part a function of how long it takes the central processing unit (CPU) to obtain data and program instructions from the memory. Programs often include one or more subroutines, or groups of instructions that are executed frequently. In other cases, the program may repeatedly use specific items of data. Thus it is desirable to store frequently used instructions and data in a manner that minimizes the time required for the central processing unit to obtain them.
A common technique to provide faster access to frequently used information uses a "cache memory". Typically, the CPU is the only device that may access the cache memory and is connected to the memory in a manner that facilitates access. When the central processing unit executes a new task, the first instruction or data item is fetched from the main memory medium. Other instructions or data in adjacent main storage locations may also be fetched at that time. The fetched instructions or data are placed in a first random access memory device of the cache memory. The cache memory has a second random access memory device which stores a "tag" that indicates whether information from a given address of the main memory is present in the cache.
Thereafter each time the central processing unit needs an item of data or a new instruction, the corresponding address for the main memory is applied to the cache memory. The address is used to read a tag from the second memory device and the tag is inspected to determine whether the requested information is present in the cache. If that information is present, the first random access memory device is enabled to send the item to the central processing unit. If the requested information is not contained in the cache, the address is sent to the main memory to obtain the information item. Once the new item has been obtained it is placed in the cache memory, as well as being sent to the central processing unit.